1) Field
Embodiments of the present invention pertain to the field of thin-film plasma etching and, in particular, to multi-film stack plasma etching with polymer passivation.
2) Description of Related Art
Recent efforts towards scaling the dimensions of semiconductor devices have include highly integrated film stack having a multiplicity of thin film layers. Such multi-film stacks find wide utility in wide array of microelectronic devices, such microprocessors, volatile and non-volatile memories, MEMS, and three-dimensionally integrated active device structures in which the vertical dimension is added to the lateral dimensions to increase the level of device integration via vertically adjacent active devices. For example, a first transistor or memory cell may be integrated with a second transistor or memory cell disposed above the first in a manner such that one or more patterned features (e.g., a gate stack, wordline, etc.) may be shared between them.
While such vertically integrated multi-film stacks may be advantageous for a number of reasons, such multi-film stacks generally can increase the complexity of etch processes used to pattern such stacks with a particular masking pattern.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or analogous elements.